DS90UH928Q-Q1 Datasheet, PDF (14/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
RIN
DCA, DCB
TxCLKOUT
START
STOP
BIT SYMBOLN BIT
START
STOP
BIT SYMBOLN+1 BIT
START
STOP
BIT SYMBOLN+2 BIT
START
STOP
BIT SYMBOLN+3 BIT
t_DD
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Latency Delay
PDB
VILmax
RIN
LOCK
PASS
TxCLKOUT
TxOUT[3:0]
X
t_TPDD
Z
Z
Z
Z
Figure 5. FPD-Link & LVCMOS Power Down Delay
PDB
LOCK
OEN
TxCLKOUT
TxOUT[3:0]
t_TXZR
VIHmin
Z
Z
Figure 6. FPD-Link Outputs Enable Delay
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PDB
VIH(min)
RIN±
LOCK
t_DDLT
TRI-STATE
Figure 7. CML PLL Lock Time
VOH(min)
14
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