DS90UH928Q-Q1 Datasheet, PDF (23/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
Feature Description (continued)
8.3.10.2 Color Modes
By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue
outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 8). In 18-bit
mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least
significant bits are 0.
8.3.10.3 Video Timing Modes
The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern
Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not
present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel
clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator
uses custom video timing as configured in the control registers. The internal timing generation may also be
driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with
External Clock are enabled by the control registers (Table 8). If internal clock generation is used, register 0x39
bit 1 must be set.
8.3.10.4 External Timing
In external timing mode, the pattern generator passes the incoming DE, HS, and VS signals unmodified to the
video control outputs after a two-pixel clock delay. It extracts the active frame dimensions from the incoming
signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS
signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without
DE asserted.
8.3.10.5 Pattern Inversion
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes
the output pattern to be bitwise-inverted. For example, the full-screen Red pattern becomes full-screen cyan, and
the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.
8.3.10.6 Auto Scrolling
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of
enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may
appear in any order in the sequence and may also appear more than once.
8.3.10.7 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA — Table 8) and the Pattern Generator Indirect Data
(PGID — Table 8).
8.3.11 Image Enhancement Features
Several image enhancement features are provided. The White Balance LUTs allow the user to define and map
the color profile of the display. Adaptive Hi-FRC Dithering enables the presentation of 'true color' images on an
18-bit display.
8.3.11.1 White Balance
The White Balance feature enables similar display appearance when using LCD’s from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, and B to
maintain specified color temperature. Programmable control registers are used to define the contents of three
LUTs (8-bit color value for Red, Green and Blue) for the White Balance Feature. The LUTs map input RGB
values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256
entries, 8-bits per entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable.
Calibrated values are loaded into registers through the I2C interface (deserializer is a slave device). This feature
may also be applied to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is
enabled and configured via serial control bus register.
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