DS90UH928Q-Q1 Datasheet, PDF (46/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
www.ti.com
Register Maps (continued)
Table 8. Serial Control Bus Registers^{(1) (2)} (continued)
ADD
(dec)
34
35
ADD
(hex)
Register Name
Bit
0x22 Data Path
7
Control
6
5
4
3
2
1
0
0x23 Rx Mode Status 7
6:4
3
2
1
0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
Default
(hex)
0x00
0x10
Function Description
Override FC Override Configuration Loaded by Forward Channel
Configuratio 0: Allow forward channel loading of this register
n
(default)
1: Disable loading of this register from the forward
channel, keeping locally written values intact
Bits [6:0] are RW if this bit is set
Pass RGB
Pass RGB on DE
Setting this bit causes RGB data to be sent
independent of DE in DS90UH928, which can be
used to allow DS90UH928 to interoperate with
DS90UB925 and DS90UB926. However, setting this
bit prevents HDCP operation and blocks packetized
audio. This bit does not need to be set in Backward
Compatibility mode.
0: Normal operation (default)
1: Pass RGB independent of DE
DE Polarity
This bit indicates the polarity of the DE (Data Enable)
signal.
0: DE is positive (active high, idle low) (default)
1: DE is inverted (active low, idle high)
I2S
Repeater
Regen
Regenerate I2S Data From Repeater I2S Pins
0: Output packetized audio on RGB video output pins.
(default)
1: Repeater regenerates I2S from I2S pins
I2S
Channel B
Enable
Override
I2S Channel B Override
0: Set I2S Channel B Disabled (default)
1: Set I2S Channel B Enable from register
18-bit Video Video Color Depth Mode
Select
0: Select 24-bit video mode (default)
1: Select 18-bit video mode
I2S
Transport
Select
Select I2S Transport Mode
0: Enable I2S Data Island Transport (default)
1: Enable I2S Data Forward Channel Frame
Transport
I2S
Channel B
Enable
I2S Channel B Enable
0: I2S Channel B disabled (default)
1: Enable I2S Channel B
RGB
Checksum
Enable
Rx RGB Checksum Enable
Setting this bit enables the Receiver to validate a one-
byte checksum following each video line. Checksum
failures are reported in the HDCP_STS register.
0: Disabled (default)
1: Enabled
Reserved
LFMODE
Status
Low Frequency Mode (LFMODE) pin status
0: 15 MHz ≤ TxCLKOUT ≤ 85 MHz (default)
1: 5 MHz ≤ TxCLKOUT < 15 MHz
REPEAT
Status
Repeater Mode (REPEAT) pin Status
0: Non-repeater (default)
1: Repeater
BKWD
Status
Backward Compatible Mode (BKWD) Status
0: Compatible to DS90UH925Q-Q1/DS90UH927Q-Q1
(default)
1: Backward compatible to DS90UR905/7Q
I2S
Channel B
Status
I2S Channel B Mode (I2S_DB) Status
0: I2S_DB inactive (default)
1: I2S_DB active
46
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