DS90UH928Q-Q1 Datasheet, PDF (6/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
www.ti.com
Pin Functions (continued)
NAME
LOCK
PIN
NO.
27
I/O, TYPE
O, LVCMOS
PASS
28
O, LVCMOS
FPD-LINK III SERIAL INTERFACE
CMF
42
Analog
CMLOUTN
45
O, LVDS
CMLOUTP
44
O, LVDS
RIN-
41
I/O, LVDS
RIN+
40
I/O, LVDS
POWER AND GROUND⁽¹⁾
GND
DAP
VDD33_A
38
VDD33_B
31
VDDIO
6
REGULATOR CAPACITOR
CAPI2S
2
CAPLV25
25
CAPLV12
29
CAPR12
46
CAPP12
47
CAPL12
33
OTHER
RES[1:0]
39, 34
Ground
Power
Power
CAP
CAP
GND
DESCRIPTION
LOCK Status Output
0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states
controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.
1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL
Route to test point or pad (Recommended). Float if unused.
PASS Status Output
0: One or more errors were detected in the received BIST payload (BIST Mode)
1: Error-free transmission (BIST Mode)
Route to test point or pad (Recommended). Float if unused.
Common Mode Filter
Requires a 0.1 µF capacitor to GND
Inverting Loop-through Driver Output
Monitor point for equalized forward channel differential signal. Connect a 100 Ω resistor
between CMLOUTN and CMLOUTP pins to monitor.
True Loop-through Driver Output
Monitor point for equalized forward channel differential signal. Connect a 100 Ω resistor
between CMLOUTN and CMLOUTP pins to monitor.
FPD-Link III Inverting Input
The output must be AC-coupled with a 0.1 µF capacitor. This pin has 100 Ω (typ.) internal
termination between RIN- and RIN+ pins.
FPD-Link III True Input
The output must be AC-coupled with a 0.1 µF capacitor. This pin has 100 Ω (typ.) internal
termination between RIN- and RIN+ pins.
Large metal contact at the bottom center of the device package
Connect to the ground plane (GND) with at least 9 vias
3.3 V Power to on-chip regulator
Each pin requires a 4.7 µF capacitor to GND
1.8 V/3.3 V LVCMOS I/O Power
Requires a 4.7 µF capacitor to GND
Decoupling capacitor connection for on-chip regulator
Each requires a 4.7 µF decoupling capacitor to GND
Decoupling capacitor connection for on-chip regulator
Requires two 4.7 µF decoupling capacitors to GND
Reserved
Connect to GND
(1) The V_DD (V_DD33 and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
6
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