DS90UH928Q-Q1 Datasheet, PDF (58/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
www.ti.com
9.2.2.2 Display Application
The DS90UH928Q-Q1, in conjunction with the DS90UH925Q-Q1 or DS90UH927Q-Q1, is intended for interfacing
with a HDCP compliant host (graphics processor) and a display supporting 24-bit color depth (RGB888) and
high-definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85
MHz together with three control bits (VS, HS, and DE) and four I2S audio streams. The included HDCP 1.3
compliant cipher block allows the authentication of the HDCP Deserializer, which decrypts both video and audio
contents. The HDCP keys are pre-loaded by TI into Non-Volatile Memory (NVM) for maximum security.
9.2.3 Application Curves
Input to Serializer
Output at Deserializer
Figure 41. 78-MHz Clock at Serializer and Deserializer
Figure 42. CMLOUT of Deserializer from 48 MHz Input
Clock
9.3 AV Mute Prevention
The DS90UH928Q-Q1 may inadvertently enter the AV MUTE state if the serializer sends video data during
blanking period (DE = L) with a specific data pattern (24’h666666). Once the device enters the AV MUTE state,
the device mutes both audio and video outputs resulting in a black display screen. Setting the gate DE Register
0x04[4] on the serializer will prevent video signals from being sent during the blanking interval. This will ensure
AV MUTE mode is not entered during normal operation.
If unexpected AV MUTE state is seen, it is recommended to verify checking the data path control setting of the
paired Serializer. This setting is not accessible from DS90UH928Q-Q1.
9.4 OEN Toggling Limitation
EON should be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN
function is asynchronous signal to the internal digital blocks, repeated by OEN toggling may result in horizontal
pixel shift at the LVDS output. TO avoid this, recommend to reset by programming Register 0x01[0] for digital
blocks after OEN turn to ON state.
10 Power Supply Recommendations
10.1 Power Up Requirements and PDB Pin
When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before
the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs
(VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not
controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs
have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or
VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.
A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.
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