DS90UH928Q-Q1 Datasheet, PDF (29/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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I2S_WC
I2S_CLK
DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
I2S_Dx
MSB
LSB MSB
LSB
Figure 25. I2S Frame Timing Diagram
When paired with a DS90UH925Q-Q1, the DS90UH928Q-Q1 I2S interface supports a single I2S data output
through I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18-bit video mode).
8.3.16.1 I2S Transport Modes
By default, packetized audio is received during video blanking periods in dedicated data island transport frames.
The transport mode is set in the serializer and auto-loaded into the deserializer by default. The audio
configuration may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired.
In frame transport, only I2S_DA is received to the DS90UH928Q-Q1 deserializer. Surround Sound Mode, which
transmits all four I2S data inputs (I2S_D[D:A]), may only be operated in Data Island Transport mode. This mode
is only available when connected to a DS90UH927Q-Q1 serializer. If connected to a DS90UH925Q-Q1serializer,
only I2S_DA and I2S_DB may be received.
8.3.16.2 I2S Repeater
I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via data
island transport on the FPD-Link interface during the video blanking periods. If frame transport is desired,
connect the I2S pins from the deserializer to all serializers. Activating surround-sound at the top-level serializer
automatically configures downstream serializers and deserializers for surround-sound transport utilizing Data
Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be explicitly
set in each serializer and deserializer control register throughout the repeater tree (Table 8).
A DS90UH928Q-Q1 deserializer configured in repeater mode may also regenerate I2S audio from its I2S input
pins in lieu of data island frames. See the HDCP Repeater Connection Diagram (Figure 31) and the I2C Control
Registers (Table 8) for additional details.
8.3.16.3 I2S Jitter Cleaning
The DS90UH928Q-Q1 features a standalone PLL to clean the I2S data jitter, supporting high-end car audio
systems. If I2S_CLK frequency is less than 1MHz, this feature must be disabled through register 0x2B[7]. See
Table 8.
8.3.16.4 MCLK
The deserializer has an I2S Master Clock Output (MCLK). It supports ×1, ×2, or ×4 of I2S CLK Frequency. When
the I2S PLL is disabled, the MCLK output is off. Table 4 covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are ×2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 8. To select
desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.
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