DS90UH928Q-Q1 Datasheet, PDF (53/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
Register Maps (continued)
Table 8. Serial Control Bus Registers^{(1) (2)} (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
192 0xC0 HDCP Debug 1 7
0x00
Reserved
6
R
HDCP
Timeout
Disable
HDCP I2C Timeout Disable
Setting this bit to a 1 will disable the bus timeout
function in the HDCP I2C master. When enabled, the
bus timeout function allows the I2C master to assume
the bus is free if no signaling occurs for more than 1
second.
Set via the HDCP_DBG register in the HDCP
Transmitter.
5:4
Reserved
3
R
RGB
Checksum
Enable
Enable RBG video line checksum
Enables sending of ones-complement checksum for
each 8-bit RBG data channel following end of each
video data line.
Set via the HDCP_DBG register in the HDCP
Transmitter.
2
R
Fast LV
Fast Link Verification
HDCP periodically verifies that the HDCP Receiver is
correctly synchronized. Setting this bit will increase
the rate at which synchronization is verified. When set
to a 1, Pj is computed every 2 frames and Ri is
computed every 16 frames. When set to a 0, Pj is
computed every 16 frames and Ri is computed every
128 frames.
Set via the HDCP_DBG register in the HDCP
Transmitter.
1
R
Timer
Speedup
Timer Speedup
Speed up HDCP authentication timers.
Set via the HDCP_DBG register in the HDCP
Transmitter.
0
R
HDCP I2C
Fast
HDCP I2C Fast mode Enable
Setting this bit to a 1 will enable the HDCP I2C Master
in the HDCP Receiver to operation with Fast mode
timing. If set to a 0, the I2C Master will operation with
Standard mode timing.
Set via the HDCP_DBG register in the HDCP
Transmitter.
193 0xC1 HDCP Debug 2 7:2
0x00
Reserved
1
RW
No Decrypt
Disable HDCP Decryption
When disabled, the HDCP Receiver will output
encrypted RGB data. This provides a simple method
for verifying that the link is encrypted.
0: HDCP Decryption enabled
1: HDCP Decryption disabled
0
Reserved
196 0xC4 HDCP Status
7:2
0x00
Reserved
1
R
RGB
Checksum
ERR
RGB Checksum Error Detected
If RGB Checksum in enabled through the HDCP
Transmitter HDCP_DBG register, this bit will indicate
if a checksum error is detected. This register may be
cleared by writing any value to this register
0
R
AUTHED
HDCP Authenticated
Indicates the HDCP authentication has completed
successfully. The controller may now send video data
requiring content protection. This bit will be cleared if
authentication is lost or if the controller restarts
authentication.
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