DS90UH928Q-Q1 Datasheet, PDF (33/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
8.4.3 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (Table 8) or by the LFMODE Pin. This mode optimizes device operation for
lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE=0, default), the
TxCLKOUT± PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High (LFMODE=1), the
TxCLKOUT± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB
reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by
four. Thus, for the operating range of 5 MHz to <15 MHz, the line rate is 700 Mbps to <2.1 Gbps with an effective
data payload of 175 Mbps to 525 Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative
to the input data rate remains the same.
8.4.4 Mode Select (MODE_SEL)
Device configuration may be done via the MODE_SEL pin or via register (Table 7). A pullup resistor and a
pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and
V_DD33 to select one of the 9 possible selected modes. See Figure 30 and Table 6.
V_DD33
R₃
VR4
R₄
MODE_SEL
Deserializer
Copyright © 2016, Texas Instruments Incorporated
Figure 30. MODE_SEL Connection Diagram
Table 6. Configuration Select (MODE_SEL)
NO.
Ideal Ratio
(V_R4/V_DD33)
Ideal
V_R4 (V)
Suggested
Resistor R₃
(kΩ, 1% tol)
Suggested
Resistor R₄
(kΩ, 1% tol)
1
0
0
OPEN
40.2
2
0.120
0.397
29.4
4.02
3
0.164
0.540
25.5
4.99
4
0.223
0.737
26.7
7.68
5
0.286
0.943
25.5
10.2
6
0.365
1.205
22.6
13.0
7
0.446
1.472
20.5
16.5
8
0.541
1.786
16.2
19.1
9
0.629
2.075
12.4
21.0
REPEAT
L
L
H
H
L
L
H
H
L
BKWD
L
L
L
L
L
L
L
L
H
I2S_B
L
H
L
H
L
H
L
H
L
LCBL
L
L
L
L
H
H
H
H
L
8.4.5 Repeater Connections
The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP
Transmitter Figure 31.
1. Video Data – Connect all FPD-Link data and clock pairs
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33 or V_DDIO = 3 V to 3.6 V with
4.7 kΩ resistors.
3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. REPEAT & MODE_SEL pins — All Transmitters and Receivers must be set into Repeater Mode.
6. Interrupt pin – Connect DS90UH928Q-Q1 INTB_IN pin to the DS90UH927Q-Q1 INTB pin. The signal must
be pulled up to V_DDIO with a 10 kΩ resistor.
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