DS90UH928Q-Q1 Datasheet, PDF (4/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
6 Pin Configuration and Functions
RHS Package
48-Pin WQFN
Top View
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I2S_DC/GPIO2 37
VDD33_A 38
RES1 39
RIN+ 40
RIN- 41
CMF 42
BISTC/INTB_IN 43
CMLOUTP 44
CMLOUTN 45
CAPR12 46
CAPP12 47
MODE_SEL 48
DS90UH928Q-Q1
TOP VIEW
DAP = GND
24 TxOUT0-
23 TxOUT0+
22 _TxOUT1-
21 _TxOUT1+
20 _TxOUT2-
19 _TxOUT2+
18 _TxCLKOUT-
17 TxCLKOUT+
16 ^TxOUT3-
15 TxOUT3+
14 GPIO0/SWC
13 GPIO1/SDOUT
Pin Functions
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
FPD-LINK OUTPUT INTERFACE
TxCLKOUT-
18
O, LVDS Inverting LVDS Clock Output
The pair requires external 100 Ω differential termination for standard LVDS levels
TxCLKOUT+
17
O, LVDS True LVDS Clock Output
The pair requires external 100 Ω differential termination for standard LVDS levels
TxOUT[3:0]-
16, 20, 22,
24
O, LVDS Inverting LVDS Data Outputs
Each pair requires external 100 Ω differential termination for standard LVDS levels
TxOUT[3:0]+ 15, 19, 21,
23
O, LVDS True LVDS Data Outputs
Each pair requires external 100 Ω differential termination for standard LVDS levels
LVCMOS INTERFACE
GPIO[1:0]
13, 14
I/O, LVCMOS General Purpose IO
with pulldown Shared with SDOUT, SWC
GPIO[3:2]
36, 37
I/O, LVCMOS General Purpose I/O
with pulldown Shared with I2S_DA I2S_WC
4
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