DS90UH928Q-Q1 Datasheet, PDF (28/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
www.ti.com
The input value present on GPIO[3:0] may also be read from register, or configured to local output mode
(Table 8).
8.3.15.2 GPIO[8:5]
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local
register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into
GPIO_REG mode. See Table 3 for GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register
access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not
transported from serializer to deserializer as is the case for GPIO[3:0].
DESCRIPTION
GPIO_REG8
GPIO_REG7
GPIO_REG6
GPIO_REG5
GPIO3
GPIO2
GPIO1
GPIO0
Table 3. GPIO_REG and GPIO Local Enable and Configuration
REGISTER CONFIGURATION
0x21 = 0x01
0x21 = 0x09
0x21 = 0x03
0x21 = 0x01
0x21 = 0x09
0x21 = 0x03
0x20 = 0x01
0x20 = 0x09
0x20 = 0x03
0x20 = 0x01
0x20 = 0x09
0x20 = 0x03
0x1F = 0x01
0x1F = 0x09
0x1F = 0x03
0x1E = 0x01
0x1E = 0x09
0x1E = 0x03
0x1E = 0x01
0x1E = 0x09
0x1E = 0x03
0x1D = 0x01
0x1D = 0x09
0x1D = 0x03
FUNCTION
Output, L
Output, H
Input, Read: 0x6F[0]
Output, L
Output, H
Input, Read: 0x6E[7]
Output, L
Output, H
Input, Read: 0x6E[6]
Output, L
Output, H
Input, Read: 0x6E[5]
Output, L
Output, H
Input, Read: 0x6E[3]
Output, L
Output, H
Input, Read: 0x6E[2]
Output, L
Output, H
Input, Read: 0x6E[1]
Output, L
Output, H
Input, Read: 0x6E[0]
8.3.16 I2S Audio Interface
The DS90UH928Q-Q1 deserializer features six I2S output pins that, when paired with a DS90UH927Q-
Q1serializer, supports surround-sound audio applications. The bit clock (I2S_CLK) supports frequencies between
1 MHz and the smaller of <PCLK/2 or <13 MHz. Four I2S data outputs carry two channels of I2S-formatted
digital audio each, with each channel delineated by the word select (I2C_WC) input. The I²S audio interface is
not available in Backwards Compatibility Mode (BKWD = 1).
Deserializer
MCLK
I2S_CLK
I2S_WC
I2S_Dx
System Clock
Bit Clock
Word Select 4
Data
I2S Receiver
Figure 24. I2S Connection Diagram
28
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Product Folder Links: DS90UH928Q-Q1