DS90UH928Q-Q1 Datasheet, PDF (37/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP

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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
Programming (continued)
The IDx pin configures the control interface to one of 10 possible device addresses. Use a pullup resistor and a
pulldown resistor to set the appropriate voltage ratio between the IDx input pin (V_R2) and V_DD33, each ratio
corresponding to a specific device address. See .
NO.
IDEAL RATIO
V_R2 / V_DD33
1
0
2
0.302
3
0.345
4
0.388
5
0.428
6
0.476
7
0.517
8
0.560
9
0.605
10
0.768
Table 7. Serial Control Bus Addresses for IDx
IDEAL V_R2
(V)
0
0.995
1.137
1.282
1.413
1.570
1.707
1.848
1.997
2.535
SUGGESTED
RESISTOR R1 kΩ
(1% tol)
OPEN
22.6
21.5
20.0
18.7
17.4
15.4
15.0
13.7
9.09
SUGGESTED
RESISTOR R2 kΩ
(1% tol)
40.2
9.76
11.3
12.7
14.0
15.8
16.5
19.1
21.0
30.1
ADDRESS 7'b
0x2C
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
ADDRESS 8'b
0x58
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 36.
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 36. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus LOW. If the address doesn't
match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled HIGH.
ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the master is reading data, the master ACKs after every
data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 37 and a WRITE is shown in Figure 38.
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
AA
21
A
0
1
c
k
Data
a
c
k
P
Figure 37. Serial Control Bus — READ
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 38. Serial Control Bus — WRITE
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