SMJ320C40_15 Datasheet, PDF (55/65 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for timer pin (see Note 13 and Figure 27)
NO.
1 t_su(TCLK-H1L)
Setup time, TCLK before H1 low
2 t_h(H1L-TCLK)
Hold time, TCLK after H1 low
3 t_d(H1H-TCLK)
Delay time, TCLK valid after H1 high
NOTE 13: Period and polarity of valid logic level are specified by contents of internal control registers.
’320C40-40
’320C40-50
’320C40-60
MIN MAX
10
0
13
UNIT
ns
ns
ns
H3
H1
2
3
1
Peripheral Pin
(TCLK)
Figure 27. Timer Pin Timing Cycle
timing for IEEE 1149.1 test-access port (see Figure 28)
NO.
1 t_su(TMS-TCKH)
2 t_h(TCKH-TMS)
3 t_d(TCKL-TDOV)
Setup time, TMS/TDI before TCK high
Hold time, TMS/TDI after TCK high
Delay time, TCK low to TDO valid
3
’320C40-40
’320C40-50
’320C40-60
MIN MAX
10
5
0
15
UNIT
ns
ns
ns
TCK
TMS/TDI
TDO
1
3
2
Figure 28. JTAG Emulation Timings
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