SMJ320C40_15 Datasheet, PDF (34/65 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
signal transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V, and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level
at which the output is said to be no longer low is 1 V, and the level at which the output is said to be high is 2 V.
See Figure 6.
2.4 V
2V
1V
0.6 V
Figure 6. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 2 V, and
the level at which the input is said to be low is 0.8 V. For a low-to-high transition on an input signal, the level at
which the input is said to be no longer low is 0.8 V, and the level at which the input is said to be high is 2 V. See
Figure 7.
2.4 V^†
2V
†
Exceptions:
X2
CLKIN
V_IH
=
3.12
V
and
CSTRBx,
CRDYx,
CREQx
and
CACKx
V_IH
=
2.64
V.
Figure 7. TTL-Level Inputs
0.8 V
0.4 V
Timing measurements, excluding TR, TF, and T disable (output going to high impedance or an I/O output
becoming an input), are referenced from an input trip point of 1.5 V to an output trip point of 2 V. Timing
measurements from H1 and H3 are referenced from 2 V on the rising or falling edges. TR and TF times are
referenced from 20% below V_OH minimum to 20% above V_OL maximum. T disable times are referenced from
an input trip point of 1.5 V to 0.1 V below V_OH (TPHZ) or above V_OL (TPLZ). The I_OL and I_OH load current can
be increased to reduce the RC time constant during TPHZ and TPLZ testing.
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