SMJ320C40_15 Datasheet, PDF (51/65 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
communication-port byte timing parameters (write and read) (see Note 12 and Figure 24)
’320C40-40
’320C40-50
NO.
’320C40-60 ^UNIT
MIN MAX
1 t_su(CD-CSL)W
Setup time, CxDx data valid before CSTRBx low (write)
2
ns
2 t_{d(CRDYL-CSH)W}
Delay time, CRDYx low to CSTRBx high (write)
0*
12 ns
3 t_h(CRDYL-CD)W
Hold time, CxDx after CRDYx low (write)
1
ns
4 t_{d(CRDYH-CSL)W}
5 t_c(BYTE)†
Delay time, CRDYx high to CSTRBx low for subsequent bytes (write)
Cycle time, byte transfer
0*
12 ns
44 ns
6 t_{d(CSL-CRDYL)R}
Delay time, CSTRBx low to CRDYx low (read)
0*
10 ns
7 t_su(CSH-CD)R
Setup time, CxDx valid after CSTRBx high (read)
0
ns
8 t_h(CRDYL-CD)R
Hold time, CxDx valid after CRDYx low (read)
2
ns
9 t_{d(CSH-CRDYH)R}
Delay time, CSTRBx high to CRDYx high (read)
0*
10 ns
† _{tc(BYTE) max = (© + £ + ¥ + ¨) where boxed numbers refer to the max values for corresponding parameters in the above table (for example,}
¥ means the value under max for parameter 6 in the table — a value of 10 ns). This assumes that two ’C40s are connected.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 12: Communication port timing does not include line length delay.
CREQx
CACKx
CSTRBx
1
CxDx
CRDYx
5
2
Valid Data
3
4
(a) WRITE TIMING
5
7
9
Valid
8
6
(b) READ TIMING
= when signal is an input (clear = when signal is an output)
Figure 24. Communication-Port Byte Timing (Write and Read)
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