SMJ320C40_15 Datasheet, PDF (49/65 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for IACK (see Note 10 and Figure 22)
NO.
’320C40-40
’320C40-50
’320C40-60
UNIT
MIN MAX MIN MAX
1 t_d(H1H-IACKL)
2 t_d(H1L-IACKH)
Delay time, H1 high to IACK low
Delay time, H1 low to IACK high during first cycle of IACK instruction
data read
9
7 ns
9
7 ns
NOTE 10: The IACK output is active for the entire duration of the bus cycle and, therefore, is extended if the bus cycle utilizes wait states.
Fetch IACK
Instruction
Decode IACK
Instruction
IACK Data
Read
Execute IACK
Instruction
H3
H1
IACK
1
2
ADDRESS
DATA
Figure 22. IACK Timing
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