SMJ320C40_15 Datasheet, PDF (52/65 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for communication-token transfer sequence, input to an output port [P = t_c(H)]^†
(see Figure 25)
’320C40-40*
’320C40-50*
NO.
’320C40-60^*
UNIT
1^† t_d(CAL-CS)T
2^† t_d(CAL-CRQH)T
MIN
MAX
Delay time, CACKx low to CSTRBx change from input to a high-level output 0.5P+ 6 1.5P+ 22 ns
Delay time, CACKx low to start of CREQx going high for token-request
acknowledge
P + 5 2P + 26 ns
3 t_d(CRQH-CRQ)T
4 t_d(CRQH-CA)T
Delay time, start of CREQx going high to CREQx change from output to an input 0.5P -- 5 0.5P+ 13 ns
Delay time, start of CREQx going high to CACKx change from an input to an
output level high
0.5P -- 5
0.5P+13
ns
4.1 t_d(CRQH-CD)T
Delay time, start of CREQx going high to CxD7--CxD0 change from inputs
driven to outputs driven
0.5P -- 5
0.5P+13
ns
4.2 t_{d(CRQH-CRDY)T}
Delay time, start of CREQx going high to CRDYx change from an output to an
input
0.5P -- 5
0.5P+13
ns
5 t_d(CRQH-CSL)T
Delay time, start of CREQx going high to CSTRBx low for start of word transfer
out
1.5P -- 8
1.5P+ 9
ns
6 t_{d(CRDYL-CSL)T}
Delay time, CRDYx low at end of word input to CSTRBx low for word output 3.5P+12 5.5P+ 48 ns
† _{These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal}
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
3
CREQx
CACKx
CSTRBx
2
4
1
5
CxD7--CxD0
CRDYx
4.1
6
Valid Data Out
4.2
= when signal is an input (clear = when signal is an output)
NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the SMJ320C40 that is receiving data. CACKx,
CSTRBx, and CxD7--CxD0 are input signals asserted by the device sending data to the ’C40; these are asynchronous with respect to
the H1 clock of the receiving SMJ320C40. After token exchange, CACKx, CSTRBx, and CxD7--CxD0 become output signals, and
CREQx and CRDYx become inputs.
Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P=t_c(H)]
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