SMJ320C40_15 Datasheet, PDF (37/65 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for a memory read/write [(L)STRBx = 0] (see Note 6, Figure 10, and Figure 11)
320C40-40
NO.
MIN MAX
1 t_d(H1L-SL)
Delay time, H1 low to (L)STRBx low
0*
10
2 t_d(H1L-SH)
Delay time, H1 low to (L)STRBx high
0*
10
3 t_d(H1H-RWL)
Delay time, H1 high to (L)R/Wx low
0*
9
4 t_d(H1L-A)
Delay time, H1 low to (L)Ax valid
0*
10
5 t_su(D-H1L)R
Setup time, (L)Dx valid before H1 low (read)
15
6 t_h(H1L-D)R
Hold time, (L)Dx after H1 low (read)
0
7 t_{su[(L)RDY-H1L]}
Setup time, (L)RDYx valid before H1 low
25
8 t_{h[H1L-(L)RDY]}
Hold time, (L)RDYx after H1 low
0
8.1 t_d(H1L-ST)
Delay time, H1 low to (L)STAT3--(L)STAT0 valid
10
9 t_d(H1H-RWH)W
Delay time, H1 high to (L)R/Wx high (write)
9
10 t_v(H1L-D)W
Valid time, (L)Dx after H1 low (write)
16
11 t_h(H1H-D)W
Hold time, (L)Dx after H1 high (write)
0
12 t_d(H1H-A)
Delay time, H1 high to address valid on back-to-back
write cycles
13
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 6: For consecutive reads, (L)R/Wx stays high and (L)STRBx stays low.
320C40-50
MIN MAX
0*
10
0*
10
0*
9
0*
9
10
0
20
0
10
9
16
0
13
320C40-60
MIN MAX
0*
8
0*
8
0*
8
0*
8
9
0
18*
0
8
0*
8
13
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8 ns
H3
H1
1
2
(L)STRBx
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STAT3--(L)STAT0
4
5
3
6
8
7
8.1
Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]
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