SMJ320C40_15 Datasheet, PDF (50/65 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
communication-port word-transfer cycle timing [P=t_c(H)] (see Note 11 and Figure 23)
’320C40-40^†
’320C40-50^†
NO.
’320C40-60^†
UNIT
MIN
MAX
1 t_{c(WORD)‡}
Cycle time, word transfer (4 bytes = 1 word)
1.5P+7 2.5P+17 ns
2 t_{d(CRDYL-CSL)W*}
Delay time, CRDYx low to CSTRBx low between back-to-back write cycles
1.5P+7 2.5P+28 ns
† _{For these timing values, it is assumed that the SMJ320C40 that is to receive data is ready to receive data.}
‡ _{tc(WORD) max = 2.5P + 28 ns + 4(¥) + 3(© + ¨ + £), where boxed numbers refer to the max values for corresponding parameters in the}
communication-port byte timing table on the next page (for example, ¥ means the value under max for parameter 6 in the table ---- a value of
10 ns). This timing assumes that two ’C40s are connected.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 11: These timings apply only to two communicating ’C4xs. When a non-’C4x device communicates with a ’C40, timings can be longer. No
restriction exists in this case on how slow the transfer could be except when using early silicon (’C40 P6 1.x or 2.x). See the CSTRB
width restriction in Section 8.9.1 of the TMS320C4x User’s Guide (literature number SPRU063).
CREQx
CACKx
1
CSTRBx
CxD7--CxD0
CRDYx
B0
B1
B2
B3
Undef. B0 (see Note B)
2
= when signal is an input (clear = when signal is an output)
NOTES: A. For correct operation during token exchange, the two communicating SMJ320C40s must have CLKIN frequencies within a factor
of 2 of each other (in other words, at most, one of the SMJ320C40s can be twice as fast as the other).
B. Begins byte 0 of the next word
Figure 23. Communication-Port Word-Transfer-Cycle Timing [P=t_c(H)]
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