DRV8702D-Q1 Datasheet, PDF (52/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
10 Layout
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10.1 Layout Guidelines
The VM pin should be bypassed to ground using a low-ESR ceramic bypass capacitor with a recommended
value of 0.1 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground-plane connection to the GND pin of the device. The VM pin must also be bypassed to ground
using a bulk capacitor rated for VM. This capacitor can be electrolytic and must be at least 10 µF.
A low-ESR ceramic capacitor must be placed between the CPL and CPH pins. A value of 0.1 µF rated for VM is
recommended. Place this capacitor as close to the pins as possible. A low-ESR ceramic capacitor must be
placed in between the VM and VCP pins. A value of 1 µF rated for 16 V is recommended. Place this component
as close to the pins as possible.
Bypass the AVDD and DVDD pins to ground with ceramic capacitors rated for 6.3 V. Place these bypassing
capacitors as close to the pins as possible.
Use separate traces to connect the SP and SN pins to the R_(SENSE) resistor.
10.2 Layout Example
0.1 µF
1 µF
0.1 µF
GND 1
IN1 2
IN2 3
GND 4
IDRIVE 5
VDS 6
GND 7
nSLEEP 8
GND
(PPAD)
24 RSVD
23 SP
22 SN
21 SP
20 GL
19 SH
18 GH
17 GND
RSENSE
S
S
S
G
Bulk
VM
D
D
D
D
SH1
1 µF
1 µF
Figure 60. DRV8702D-Q1 Layout Example
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