DRV8702D-Q1 Datasheet, PDF (22/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.1 Bridge Control
The DRV870xD-Q1 device is controlled using a configurable input interface. The Logic Tables section provides
the half-bridge operation states. These tables do not consider the current control built into the DRV870xD-Q1
device. The logic operation set by the MODE pin is latched on power-up or when exiting sleep mode. Figure 31
shows the direction of the flow of current through the load when it is connected between the SH pin and GND,
and between the SH pin and VM.
VM
VM
1
SH
2
1 Drive
2 Slow decay (brake)
2
1
SH
Figure 31. Bridge Control
7.3.1.1 Logic Tables
Table 3, and Table 4 are the device logic tables. An X denotes a don’t care input or output.
NOTE
Any other input logic combinations, aside from the ones mentioned in Table 3 and
Table 4, result in an error, and the device will trigger a fault.
Table 3. DRV870xD-Q1 PWM Control Interface Without Current Regulation (MODE = 1)
nSLEEP
IN1
IN2
GH
GL
SH
AVDD/DVDD
Description
0
X
X
X
X
Hi-Z
Disabled
Sleep mode ½-bridge disabled
1
0
0
0
1
L
Enabled
½-bridge low side on
1
1
0
1
0
H
Enabled
½-bridge high side on
Table 4. DRV870xD-Q1 PWM Control Interface With Current Regulation (MODE = Hi-Z)
nSLEEP
IN1
IN2
GH
GL
SH
AVDD/DVDD
Description
0
X
X
X
X
Hi-Z
Disabled
Sleep mode ½-bridge disabled
1
0
0
0
0
Hi-Z
Enabled
½-bridge is in tri-state
1
1
0
1
0
H
Enabled
½-bridge high-side on
1
1
1
0
1
L
Enabled
½-bridge low-side on
If MODE = Hi-Z is selected, the device performs current regulation (refer to the Current Regulation section).
Having both the input (INx) pins high puts the motor in brake mode (low-side slow decay). If MODE = 1 is
selected, current regulation is disabled and must be performed externally using a MCU. With MODE = 1, the load
current recirculation occurs through the high-side FET as shown in Figure 31.
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