DRV8702D-Q1 Datasheet, PDF (10/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A = 25°C and V_VM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRV8702D and DRV8703D VREF_SCL =
00 (100%)
1
MΩ
R_VREF
VREF input impedance
DRV8703D VREF_SCL = 2’b01, 2’b10 or
2’b11
175
kΩ
A_V
Amplifier gain (DRV8702D-Q1) 60 < V_SP < 225 mV; V_SN = GND
19.3
19.8
20.3 V/V
GAIN_CS = 00; 10 < V_SP < 450 mV; V_SN
= GND
9.75
10 10.25
GAIN_CS = 01; 60 < V_SP < 225 mV; V_SN
= GND
19.3
19.8
20.3
A_V
Amplifier gain (DRV8703D-Q1)
GAIN_CS = 10; 10 < V_SP < 112 mV; V_SN
= GND
V/V
38.4
39.4
40.4
GAIN_CS = 11; 10 < V_SP < 56 mV; V_SN =
GND
73
78
81
V_IO
V_IO(DRIFT)
Input-referred offset
Drift offset⁽²⁾
I_SP
SP input current
V_SO
SO pin output voltage range
C_(SO)
Allowable SO pin capacitance
PROTECTION CIRCUITS
V_SP = V_SN = GND
V_SP = V_SN = GND
V_SP = 100 mV; V_SN = GND
5
10
–20
A_V × V_OFF
10 mV
µV/°C
µA
4.5 V
1 nF
V_(UVLO2)
VM undervoltage lockout
VM falling; UVLO2 report
VM rising; UVLO2 recovery
5.25
5.45
V
5.4
5.65
V_(UVLO1)
V_hys(UVLO)
Logic undervoltage lockout
VM undervoltage hysteresis
V_{(CP_UV)}
Charge pump undervoltage
Rising to falling threshold
VCP falling; CPUV report
VCP rising; CPUV recovery
100
V_VM +
1.5
V_VM +
1.55
4.5 V
mV
V
V_{hys(CP_UV)}
V_{(DS_OCP)}
CP undervoltage hysteresis
Overcurrent protection trip level,
V_DS of each external FET
(DRV8702D-Q1)
High side FETs: VDRAIN – SH
Low side FETs: SH – SP
Rising to falling threshold
R_(VDS) < 1 kΩ to GND
R_(VDS) = 33 kΩ to GND
R_(VDS) = 200 kΩ to GND
R_(VDS) > 2 MΩ to GND
R_(VDS) = 68 kΩ to AVDD
R_(VDS) < 1 kΩ to AVDD
VDS_LEVEL = 3’b000
50
mV
0.06
0.12
0.24
V
0.48
0.96
Disabled
0.06
VDS_LEVEL = 3’b001
0.145
V_{(DS_OCP)}
Overcurrent protection trip level,
V_DS of each external FET
(DRV8703D-Q1)
High-side FETs: VDRAIN – SH
Low-side FETs: SH – SP
VDS_LEVEL = 3’b010
VDS_LEVEL = 3’b011
VDS_LEVEL = 3’b100
VDS_LEVEL = 3’b101
0.17
0.2
V
0.12
0.24
VDS_LEVEL = 3’b110
0.48
VDS_LEVEL = 3’b111
0.96
V_{(SP_OCP)}
T_(OTW)
T_SD
T_hys
V_C(GS)
Overcurrent protection trip level,
measured by sense amplifier
V_SP with respect to GND
Thermal warning temperature⁽¹⁾ Die temperature T_J
Thermal shutdown temperature⁽¹⁾ Die temperature T_J
Thermal shutdown hysteresis⁽¹⁾ Die temperature T_J
Gate-drive clamping voltage
Positive clamping voltage
Negative clamping voltage
0.8
1
1.2 V
120
135
145 °C
150
°C
20
°C
16.3
17
17.8
V
–1
–0.7
–0.5
10
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1