DRV8702D-Q1 Datasheet, PDF (36/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.14.7 Watchdog Fault (WDFLT, DRV8703D-Q1 Only)
An MCU watchdog function can be enabled to ensure that the external controller that is instructing the
DRV8703D-Q1 device is active and in a known state. The SPI watchdog must be enabled by writing a 1 to the
WD_EN bit through the SPI (disabled by default, bit is 0). When the watchdog is enabled, an internal timer starts
to count down to an interval set by the WD_DLY bits. The register address 0x00 must be read by the MCU within
the interval set by the WD_DLY bit to reset the watchdog. If the timer is allowed to expire, the nWDFLT pin is
enabled. When the nWDFLT pin is enabled the following occurs:
• The nWDFLT pin goes low for 64 µs.
• The nFAULT pin is asserted.
• The WD_EN bit is cleared.
• The drivers are disabled.
The WDFLT bit remains asserted, and operation is halted until the CLR_FLT bit has been written to 1.
Table 8 lists the fault responses of the device under the fault conditions.
FAULT
VM undervoltage
(UVLO)
VCP undervoltage
(CPUV)
External FET overload
(OCP)
Gate driver fault
(GDF)
Watchdog fault
(WDFLT)
Thermal shutdown
(TSD)
Table 8. Fault Response
CONDITION
V_VM ≤ V_(UVLOx)
(5.45 V, max)
V_VCP ≤ V_{(CP_UV)}
(V_VM + 1.5, typ)
V_DS ≥ V_DS(OCP)
V_SP – V_SN > 1 V
Gate voltage unchanged after
t_(DRIVE)
Watchdog timer expires
HALF-BRIDGE
Disabled
Disabled
Disabled
Disabled
Disabled
CHARGE PUMP
Disabled
Operating
Operating
Operating
Operating
AVDD
Disabled
Operating
Operating
Operating
Operating
T_J ≥ T_SD (150°C, min)
Disabled
Disabled
Disabled
DVDD
Operating
Operating
Operating
Operating
Operating
Operating
RECOVERY
V_VM ≥ V_(UVLOx)
(5.65 V, max)
V_VCP ≥ V_{(CP_UV)}
(V_VM + 1.5, typ)
t_(RETRY)
t_(RETRY)
CLR_FLT bit
T_J ≤ T_SD – T_hys
(T_hys is typically 20°C)
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