DRV8702D-Q1 Datasheet, PDF (12/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
Switching Characteristics (continued)
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
PROTECTION CIRCUITS
t_(UVLO)
t_(OCP)
t_(RETRY)
VM UVLO falling deglitch time
Overcurrent deglitch time
Overcurrent retry time
VM falling; UVLO report
WD_DLY = 2’b00
t_(WD)
Watchdog time out (DRV8703D-
Q1)
WD_DLY = 2’b01
WD_DLY = 2’b10
WD_DLY = 2’b11
t_(RESET)
SPI
Watchdog timer reset period
t_{(SPI_READY)}
t_d(SDO)
SPI read after power on
SDO output data delay time, CLK
high to SDO valid
VM > VUVLO1
C_L = 20 pF
t_a
SCS access time, SCS low to SDO
out of high impedance
t_dis
SCS disable time, SCS high to
SDO high impedance
SCS
t HI_SCS
t SU_SCS
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MIN
TYP
MAX UNIT
10
3.7
4
2.8
3
10
20
50
100
64
µs
4.3
µs
3.2
ms
ms
µs
5
10
ms
30
ns
10
ns
10
ns
t HD_SCS
t CLK
SCLK
SDI
SDO
Z
t ACC
t CLKH
t CLKL
MSB in
(must be valid)
tSU_SDI tHD_SDI
MSB out (is valid)
LSB
LSB
t D_SDO
t HD_SDO
Figure 1. SPI Slave Mode Timing Definition
Z
t DIS
12
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