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DRV8702D-Q1 Datasheet, PDF (23/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver
www.ti.com
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
7.3.2 MODE Pin
The MODE pin of the device determines the control interface and latches on power-up or when exiting sleep
mode. Figure 32 shows an overview of the internal circuit of the MODE pin.
DVDD
MODE
26 k
65 k
+
1.35 V ±
+
0.75 V ±
Digital
Core
Figure 32. MODE Pin Block Diagram
Table 5 lists the different control interfaces that can be set via MODE pin at power-up or when exiting sleep
mode.
MODE
1
Hi-Z
Table 5. MODE Pin Configuration
CONTROL INTERFACE
PWM control interface without current regulation
PWM control interface with current regulation
During the device power-up sequence, the DVDD pin is enabled first. Then the MODE pin latches. Finally the
AVDD pin is enabled. For setting PWM control interface, TI does not recommended connecting the MODE pin to
the AVDD pin. Instead the MODE pin should be connected to an external 5-V or 3.3-V supply or to the DVDD pin
if not driven by an external microcontroller (MCU).
7.3.3 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is
detected, the nFAULT line is logic low.
nFAULT
Output
Figure 33. nFAULT Block Diagram
For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a resistor (refer to the Application and
Implementation section). For a 5-V pullup an external 5-V supply should be used. TI does not recommended
connecting the nFAULT pin to the AVDD pin.
7.3.4 Current Regulation
The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation or
current chopping. When an half-bridge is enabled, current rises through the winding at a rate dependent on the
DC voltage and inductance of the winding. When the current hits the current chopping threshold, the bridge
enters a brake (low-side slow decay) mode until the toff time expires.
Copyright © 2017, Texas Instruments Incorporated
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