DRV8702D-Q1 Datasheet, PDF (39/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

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DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
7.4 Device Functional Modes
The DRV870xD-Q1 device is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is
disabled, the half-bridge FETs are disabled to the Hi-Z state, and the AVDD and DVDD regulators are disabled.
NOTE
The t_(SLEEP) time must elapse after a falling edge on the nSLEEP pin before the device is
in sleep mode. The DRV870xD-Q1 device is brought out of sleep mode automatically if
the nSLEEP pin is brought high.
The t_(WAKE) time must elapse before the outputs change state after wakeup.
On the DRV8703D-Q1 device, the SPI settings are reset when coming out of UVLO or exiting sleep mode.
While the nSLEEP pin is brought low, both external half-bridge FETs are disabled. The high-side gate pin, GH,
are pulled to the output node, SH, by an internal resistor and the low-side gate pin, GL, are pulled to ground.
When the VM voltage is not applied and during the power-on time (t_on) the outputs are disabled using weak
pulldown resistors between the GH and SH pins and the GL and GND pins.
NOTE
The MODE pin controls the device-logic operation for phase and enable, independent half-
bridge, or PWM input modes. This operation is latched on power up or when exiting sleep
mode.
7.5 Programming
7.5.1 SPI Communication
7.5.1.1 Serial Peripheral Interface (SPI)
The SPI (DRV8703D-Q1 only) is used to set device configurations, operating parameters, and read out
diagnostic information. The DRV8703D-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists
of a 16-bit word, with a 5-bit command, 3 don't care bits, and 8 bits of data. The SPI output data (SDO) word
consists of 8-bit register data and the first 8 bits are don’t cares.
A valid frame has to meet following conditions:
• The clock polarity (CPOL) must be set to 0.
• The clock phase (CPHA) must be set to 0.
• The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
• No SCLK signal can occur when the nSCS signal is in transition.
• The SCLK pin must be low when the nSCS pin goes high.
• The nSCS pin should be taken high for at least 500 ns between frames.
• When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is
in the high impedance state.
• Full 16 SCLK cycles must occur.
• Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.
• The most-significant bit (MSB) is shifted in and out first
• For a write command, if the data word sent to the SDI pin is less than or more than 16 bits, a frame error
occurs and the data word is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5-bit command data
Copyright © 2017, Texas Instruments Incorporated
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