DRV8702D-Q1 Datasheet, PDF (27/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

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DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
7.3.6 PWM Motor Gate Drivers
The DRV870xD-Q1 device has gate drivers for a single half-bridge with external NMOS FETs. Figure 37 shows a
block diagram of the predrive circuitry.
VGHS
VM
IN
nSLEEP
Logic
Predrive
GH
R(OFF)
SH
VGLS
GL
R(OFF)
M
SP
SN
R(SENSE)
Figure 37. Predrive Block Diagram
Gate drivers inside the DRV870xD-Q1 device directly drive N-Channel MOSFETs, which drive the motor current.
The high-side gate drive is supplied by the charge pump, while an internal regulator generates the low-side gate
drive.
The peak drive current of the gate drivers is adjustable through the IDRIVE pin for DRV8702D-Q1 device or the
IDRIVE register for the DRV8703D-Q1 device. Peak source currents can be set to the values listed in the FET
gate drivers section of the Electrical Characteristics table. The peak sink current is approximately two times the
peak source current. Adjusting the peak current changes the output slew rate, which also depends on the FET
input capacitance and gate charge.
Fast switching times can cause extra noise on the VM and GND pins. This additional noise can occur specifically
because of a relatively slow reverse-recovery time of the low-side body diode, when the body diode conducts
reverse-bias momentarily, similar to shoot-through. Slow switching times can cause excessive power dissipation
because the external FETs have a longer turnon and turnoff time.
When changing the state of the output, the peak current (I_DRIVE) is applied for a short period (t_(DRIVE)), to charge
the gate capacitance. After this time, a weak current source (I_HOLD) is used to keep the gate at the desired state.
When selecting the gate drive strength for a given external FET, the selected current must be high enough to
charge fully and discharge the gate during t_(DRIVE), or excessive power is dissipated in the FET.
During high-side turnon, the low-side gate is pulled low with a strong pulldown (I_STRONG). This pulldown prevents
the low-side FET Q_GS from charging and keeps the FET off, even when fast switching occurs at the outputs.
The gate-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. When the switching FETs are on, this handshaking prevents
the high-side or low-side FET from turning on until the opposite FET turns off.
Copyright © 2017, Texas Instruments Incorporated
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