DRV8702D-Q1 Datasheet, PDF(24/66 Page) Texas Instruments

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DRV8702D-Q1 Datasheet, PDF (24/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

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DRV8702D-Q1, DRV8703D-Q1

SLVSDX8 â MARCH 2017

www.ti.com

NOTE

Immediately after the current is enabled, the voltage on the SP pin is ignored for a period

(t(BLANK)) before enabling the current-sense circuitry.

The PWM chopping current is set by a comparator that compares the voltage across a current-sense resistor

connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV

is the shunt-amplifier gain, which is 19.8 V/V for the DRV8702D-Q1 device or configurable to 10, 19.8, 39.4, or

78 V/V for the DRV8703D-Q1 device.

Use Equation 1 to calculate the chopping current (ICHOP).

I(CHOP)

VVREF VIO

AV u R(SENSE)

(1)

For example, if a 50-mÎ© sense resistor and a VREF value of 3.3 V are selected, the full-scale chopping current

is 3.28 A. The AV is 19.8 V/V and VIO is assumed to be 50 mV in this example.

NOTE

If the load is connected between the SH pin and VM and current regulation is enabled

(MODE pin is Hi-Z), the low-side FET is switched on when the current flowing through the

load exceeds the ICHOP threshold. This result in an adverse effect by driving the load at

100% duty cycle because the maximum current flows through the load as the low-side

FET remains switched on for the tOFF duration. Texas Instruments recommends using the

PWM control interface without current regulation (MODE pin is 1) for this configuration to

drive the load.

For DC motors, current regulation is used to limit the start-up and stall current of the motor. If the current

regulation feature is not needed, it can be disabled by tying the VREF pin directly to the AVDD pin. If the PWM

control-interface mode without current regulation (MODE pin is 1) is selected for operation, the device does not

perform PWM current regulation or current chopping.

7.3.5 Amplifier Output (SO)

The SO pin on the DRV870xD-Q1 device outputs an analog voltage equal to the voltage across the SP and SN

pins multiplied by AV. The SO voltage is only valid for when the load is connected in the way shown in Figure 31.

Use Equation 2 to calculate the approximate current for the half-bridge.

VSO VIO

A V u R(SENSE)

(2)

When the SP and SN voltages are 0 V, the SO pin outputs the amplifier offset voltage, VIO. No capacitor is

required on the SO pin.

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Product Folder Links: DRV8702D-Q1 DRV8703D-Q1

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