DRV8702D-Q1 Datasheet, PDF (31/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

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DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
7.3.8 Dead Time
The dead time (t_(DEAD)) is measured as the time when the SH pin is in the Hi-Z state between turning off one of
the half-bridge FETs and turning on the other. For example, the output is Hi-Z between turning off the high-side
FET and turning on the low-side FET.
The dead time consists of an inserted digital dead time and FET gate slewing. The DRV8702D-Q1 device has a
digital dead time of approximately 240 ns. The DRV8703D-Q1 device has programmable dead-time options of
120, 240, 480, 960 ns. In addition to this digital dead time, the output is Hi-Z as long as the voltage across the
GL pin to ground or GH pin to SH pin is less than the FET threshold voltage.
The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GH
and GL pins) includes the observable dead time.
7.3.9 Propagation Delay
The propagation delay time (t_PD) is measured as the time between an input edge to an output change. This time
is composed of two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on
the input pins from affecting the output state.
The gate drive slew rate also contributes to the delay time. For the output to change state during normal
operation, one FET must first be turned off. The FET gate is ramped down according to the IDRIVE resistor
selection, and the observed propagation delay ends when the FET gate falls below the threshold voltage.
7.3.10 Overcurrent VDS Monitor
The gate-driver circuit monitors the VDS voltage of each external FET when it is driving current. When the
voltage monitored is greater than the OCP threshold voltage (V_DS(OCP)) after the OCP deglitch time has expired,
an OCP condition is detected. The VDS voltage can be adjusted by changing the resistor (R_(VDS)) on the VDS pin
of the DRV8702D-Q1 device. The DRV8703D-Q1 device provides VDS voltage levels by setting the VDS
register.
+
High-Side
VDS OCP
Monitor
±
VM
VDRAIN
GH
SH
GL
+
Low-Side
VDS OCP
Monitor 1
±
SP
SN
M
R(SENSE)
Figure 41. V_DS(OCP) Block Diagram
The VDS voltage on the high-side FET is measured across the VDRAIN to SH pin. The low-side VDS monitor
measures the VDS voltage across the SH to SP pins. Ensure that the SP pin is always connected to the source
of the low-side FET of half-bridge, even when the sense amplifier is not used.
Copyright © 2017, Texas Instruments Incorporated
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