DRV8702D-Q1 Datasheet, PDF (35/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

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DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
7.3.14 Protection Circuits
The DRV870xD-Q1 device is fully protected against VM undervoltage, charge-pump undervoltage, overcurrent,
gate-driver shorts, and overtemperature events.
7.3.14.1 VM Undervoltage Lockout (UVLO2)
If the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (V_UVLO2), both FETs in the
half-bridge are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The VM_UVFL bit of
the DRV8703D-Q1 device is set. The operation resumes when the VM voltage rises above the UVLO2 threshold.
The nFAULT pin is released after the operation resumes but the VM_UVFL bit on the DRV8703D-Q1 device
remains set until cleared by writing to the CLR_FLT bit.
The SPI settings on the DRV8703D-Q1 device are not reset by this fault even though the output drivers are
disabled. The settings are maintained and internal logic remains active until the VM voltage falls below the logic
undervoltage threshold (VUVLO1).
7.3.14.2 Logic Undervoltage (UVLO1)
If the voltage on the VM pin falls below the logic undervoltage threshold voltage (V_UVLO1), the internal logic is
reset. The operation resumes when the VM voltage rises above the UVLO1 threshold. The nFAULT pin is logic
low during this state because it is pulled low when the VM undervoltage condition occurs. Decreasing the VM
voltage below this undervoltage threshold resets the SPI settings.
7.3.14.3 VCP Undervoltage Lockout (CPUV)
If the voltage on the VCP pin falls below the threshold voltage of the charge-pump undervoltage (CPUV) lockout,
both FETs in the half-bridge are disabled and the nFAULT pin is driven low. The DRV8703D-Q1 the VCP_UVFL
bit is set. The operation resumes when the VCP voltage rises above the CPUV threshold. The nFAULT pin is
released after the operation resumes but the VCP_UVFL bit on the DRV8703D-Q1 device remains set until
cleared by writing to the CLR_FLT bit.
7.3.14.4 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs. If the voltage across a
driven FET exceeds the V_DS(OCP) level for longer than the OCP deglitch time, an OCP event is recognized. Both
FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The OCP bit of the DRV8703D-Q1
device is set. The drive re-enables after the t_(RETRY) time has passed. The nFAULT pin becomes high again after
the retry time.
If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes
and the nFAULT pin goes high. The OCP bit on the DRV8703D-Q1 remains set until cleared by writing to the
CLR_FLT bit. In addition to this FET VDS monitor, an overcurrent condition is detected if the voltage at the SP
pin exceeds V_SP(OCP) and the nFAULT pin is driven low. The OCP bit in the DRV8703-Q1 device is set.
7.3.14.5 Gate Driver Fault (GDF)
The GH and GL pins are monitored such that if the voltage on the external FET gate does not increase or
decrease after the t_(DRIVE) time, a gate driver fault is detected. This fault occurs if the GH or GL pins are shorted
to the GND, SH, or VM pin. Additionally, a gate-driver fault occurs if the selected IDRIVE setting is not sufficient
to turn on the external FET. Both FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The
GDF bit of the DRV8703D-Q1 device is set. The driver re-enables after the OCP retry period (t_(RETRY)) has
passed. The nFAULT pin is released after the operation has resumed but the GDF bit on the DRV8703D-Q1
device remains set until cleared by writing to the CLR_FLT bit.
7.3.14.6 Thermal Shutdown (TSD)
If the die temperature exceeds the T_SD temperature, both FETs in the half-bridge are disabled, the charge pump
shuts down, the AVDD regulator is disabled, and the nFAULT pin is driven low. The OTSD bit of the DRV8703D-
Q1 device is set as well. After the die temperature falls below T_SD – T_hys temperature, device operation
automatically resumes. The nFAULT pin is released after the operation resumes, but the OTSD bit on the
DRV8703D-Q1 device remains set until cleared by writing to the CLR_FLT bit.
Copyright © 2017, Texas Instruments Incorporated
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