DRV8702D-Q1 Datasheet, PDF (5/66 Pages) Texas Instruments – Automotive Half-Bridge Gate Driver

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DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
Power supply voltage
Charge pump voltage
Charge pump negative switching pin
Internal logic regulator voltage
Internal analog regulator voltage
Drain pin voltage
Voltage difference between supply and
VDRAIN
Control pin voltage
High-side gate pin voltage
Low-side gate pin voltage
Continuous phase-node pin voltage
Pulsed 10-µs phase-node pin voltage
Continuous shunt amplifier input pin voltage
Pulsed 10-µs shunt amplifier input pin voltage
Shunt amplifier output pin voltage
Shunt amplifier output pin current
Maximum current, limit current with external
series resistor
Open-drain output current
Gate pin source current
Gate pin sink current
Operating junction temperature, T_J
Storage temperature, T_stg
VM
VCP, CPH
CPL
DVDD
AVDD
VDRAIN
VM – VDRAIN
IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE,
VVDS, MODE, nSCS, SCLK, SDI, SDO,
nWDFLT
GH
GL
SH
SH
SP
SN
SP
SO
SO
VDRAIN
nFAULT, SDO, nWDFLT
GH, GL
GH, GL
MIN
MAX
–0.3
47
–0.3
–0.3
–0.3
V_VM + 12
V_VM
3.8
–0.3
5.75
–0.3
47
–10
10
–0.3
5.75
–0.3
–0.3
–1.2
–2
–0.5
–0.3
–1
–0.3
0
V_VM + 12
12
V_VM + 1.2
V_VM + 2
1
0.3
1
5.75
5
–2
2
0
10
0
250
0
500
–40
150
–65
150
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V_(ESD)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002⁽¹⁾
Charged-device model (CDM), per AEC
Q100-011
All pins
Corner pins (1, 8, 9, 16, 17,
24, 25, and 32)
VALUE
±2000
±500
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
UNIT
V
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