DS90UH925Q-Q1 Datasheet, PDF (5/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Pin Functions (continued)
NAME
STATUS
INTB
PIN
NUMBER
31
I/O, TYPE
O, LVCMOS
Open Drain
FPD-Link III SERIAL INTERFACE
DOUT+
20
O, LVDS
DOUT-
19
O, LVDS
CMF
23
POWER⁽¹⁾ and GROUND
V_DD33
V_DDIO
GND
22
30
DAP
Analog
Power
Power
Ground
REGULATOR CAPACITOR
CAPHS12,
CAPP12
17, 14
CAPL12
7
CAP
CAP
OTHERS
NC
RES[1:0]
16
18, 15
NC
GND
DESCRIPTION
HDCP Interrupt
INTB = H, normal
INTB = L, Interrupt request
Recommended pull-up: 4.7kΩ to V_DDIO
True Output
The output must be AC-coupled with a 0.1µF capacitor.
Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
Common Mode Filter.
Connect 0.1µF to GND
Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
Do not connect.
Reserved. Tie to Ground.
(1) The VDD (V_DD33 and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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