DS90UH925Q-Q1 Datasheet, PDF (17/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Feature Description (continued)
7.3.13 Interrupt Pin — Functional Description and Usage (INTB)
1. On DS90UH925Q-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UH926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UH925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an
interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .
5. A read to HDCP_ISR will clear the interrupt at the DS90UH925Q-Q1, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN (pin 16) on the DS90UH926Q-Q1. The system is now ready to return to step (1) at next falling edge
of INTB_IN.
7.3.14 EMI Reduction Features
7.3.14.1 Input SSC Tolerance (SSCT)
The DS90UH925Q-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile
up to +/-2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.
7.3.14.2 GPIO[3:0] and GPO_REG[8:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH925Q-Q1 can be used as the
general purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) application.
7.3.14.2.1 GPIO[3:0] Enable Sequence
See Table 1 for the GPIO enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UH925Q-Q1 only.
DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.
Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UH925Q-Q1, then write 0x05 to
address 0x1F on DS90UH926Q-Q1.
#
DESCRIPTION
1
Enable 18-bit
mode
2
GPIO3
3
GPIO2
4
GPIO1
5
GPIO0
Table 1. GPIO Enable Sequencing Table
DEVICE
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
DS90UH925Q-Q1
DS90UH926Q-Q1
FORWARD
CHANNEL
0x12 = 0x04
Auto Load from DS90UH925Q-Q1
0x0F = 0x03
0x1F = 0x05
0x0E = 0x30
0x1E = 0x50
0x0E = 0x03
0x1E = 0x05
0x0D = 0x93
0x1D = 0x95
BACK
CHANNEL
0x12 = 0x04
Auto Load from DS90UH925Q-Q1
0x0F = 0x05
0x1F = 0x03
0x0E = 0x50
0x1E = 0x30
0x0E = 0x05
0x1E = 0x03
0x0D = 0x95
0x1D = 0x93
7.3.14.2.2 GPO_REG[8:4] Enable Sequence
GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 2
for the GPO_REG enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UH925Q-Q1 only.
DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.
Step 2: To enable GPO_REG8 outputs an “1”, write 0x90 to address 0x11 on DS90UH925Q-Q1.
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