DS90UH925Q-Q1 Datasheet, PDF (35/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
101
102
103
128
129
130
131
132
144
145
146
147
148
Table 6. Serial Control Bus Registers (continued)
ADD
(hex)
REGISTER
NAME
0x65 Pattern
Generator
Configuration
Bit(s)
7:5
4
3
2
1
0
0x66 Pattern
7:0
Generator
Indirect Address
0x67 Pattern
7:0
Generator
Indirect Data
0x80 RX_BKSV0
7:0
0x81 RX_BKSV1
7:0
0x82 RX_BKSV2
7:0
0x83 RX_BKSV3
7:0
0x84 RX_BKSV4
7:0
0x90 TX_KSV0
7:0
0x91 TX_KSV1
7:0
0x92 TX_KSV2
7:0
0x93 TX_KSV3
7:0
0x94 TX_KSV4
7:0
REG-
ISTER
TYPE
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reserved
Pattern
Generator
18 Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled
patterns will have 64 levels of brightness and the R,
G, and B outputs use the six most significant color
bits.
0: Enable 24-bit pattern generation. Scaled patterns
use 256 levels of brightness.
Pattern
Generator
External
Clock
Select External Clock Source
1: Selects the external pixel clock when using
internal timing.
0: Selects the internal divided clock when using
internal timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
Pattern
Generator
Timing
Select
Timing Select Control
1: The Pattern Generator creates its own video
timing as configured in the Pattern Generator Total
Frame Size, Active Frame Size. Horizontal Sync
Width, Vertical Sync Width, Horizontal Back Porch,
Vertical Back Porch, and Sync Configuration
registers.
0: the Pattern Generator uses external video timing
from the pixel clock, Data Enable, Horizontal Sync,
and Vertical Sync signals.
Pattern
Enable Inverted Color Patterns
Generator 1: Invert the color output.
Color Invert 0: Do not invert the color output.
Pattern
Generator
Auto-Scroll
Enable
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to
the next enabled pattern after the number of frames
specified in the Pattern Generator Frame Time
(PGFT) register.
0: The Pattern Generator retains the current pattern.
Indirect
Address
This 8-bit field sets the indirect address for
accesses to indirectly-mapped registers. It should
be written prior to reading or writing the Pattern
Generator Indirect Data register.
See AN-2198 (SNLA132)
Indirect
Data
When writing to indirect registers, this register
contains the data to be written. When reading from
indirect registers, this register contains the read
back value.
See AN-2198 ( SNLA132)
RX BKSV0 BKSV0: Value of byte 0 of the Deserializer KSV
RX BKSV1 BKSV1: Value of byte 1 of the Deserializer KSV
RX BKSV2 BKSV2: Value of byte 2 of the Deserializer KSV
RX BKSV3 BKSV3: Value of byte 3of the Deserializer KSV
RX BKSV4 BKSV4: Value of byte 4of the Deserializer KSV
TX KSV0 KSV0: Value of byte 0 of the Serializer KSV
TX KSV1 KSV1: Value of byte 1 of the Serializer KSV
TX KSV2 KSV2: Value of byte 2 of the Serializer KSV
TX KSV3 KSV3: Value of byte 3 of the Serializer KSV
TX KSV4 KSV4: Value of byte 4 of the Serializer KSV
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