DS90UH925Q-Q1 Datasheet, PDF (12/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
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6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_LHT
CML Output Low-to-High
Transition Time
t_HLT
CML Output High-to-Low
Transition Time
See Figure 4
t_DIS
Data Input Setup to PCLK
t_DIH
Data Input Hold from PCLK
See Figure 5
t_PLD
Serializer PLL Lock Time
t_SD
Delay — Latency
Output Total Jitter,
t_TJIT
Bit Error Rate ≥10^-10
Figure 7 ^{(2) (3) (4)}
Figure 6 ⁽¹⁾
R_L = 100Ω
f = 85MHz, LFMODE = L
R_L = 100Ω
f = 5MHz, LFMODE = H
DOUT+,
DOUT-
R[7:0],
G[7:0],
B[7:0],
HS, VS,
DE,
PCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
f = 5 – 85
MHz
f = 5 – 85
MHz
DOUT+,
DOUT-
MIN
TYP
MAX
80
130
80
130
2.0
2.0
131*T
145*T
0.25
0.30
0.25
0.30
(1) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.
(2) Specification is ensured by characterization and is not tested in production.
(3) Specification is ensured by design and is not tested in production.
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35*PCLK). The UI scales with PCLK frequency.
UNIT
ps
ps
ns
ns
ns
ns
UI
UI
12
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