DS90UH925Q-Q1 Datasheet, PDF (25/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
7.5 Programming
7.5.1 Serial Control Bus
The DS90UH925Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. This bus is
also used by the Host source to control and monitor status of the HDCP function. Multiple serializer devices may
share the serial control bus since 16 device addresses are supported. Device address is set via R₁ and R₂
values on IDx pin. See Figure 19 below.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pull-up resistor to V_DD33. For most applications a 4.7 k pull-up resistor to V_DD33 may be used. The resistor value
may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven
Low.
V_DD33
HOST
or
Salve _SCL
SDA
V_DD33
R₁
VR2
4.7k
4.7k
R₂
IDx
SER
or
SCL ^DES
SDA
To other
Devices
Figure 19. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 9 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (V_R2) and V_DD33 to
select one of the other 9 possible addresses. Table 5 defines the required VR2 and VR2/VDD33 ratios, and
suggests standard resistor values to achieve these ratios. In systems where excessive noise may be present, we
recommend reducing the resistor values (by a factor of 10x or 100x) while maintaining the required ratio. This
provides tighter coupling to supply rails, and more stability of VR2 in the presence of coupled noise. Note that
reducing the resistor values will increase the current consumed by the resistor divider. See Table 5.
IDEAL
#
RATIO
V_R2 / V_DD33
1
0
2
0.121
3
0.152
4
0.180
5
0.208
6
0.303
7
0.345
8
0.389
9
0.727
Table 5. Serial Control Bus Addresses for IDx
IDEAL V_R2
(V)
0
0.399
0.502
0.594
0.685
0.999
1.137
1.284
2.399
SUGGESTED
RESISTOR
R1 kΩ (1% tol)
Open
294
280
137
118
115
102
115
90.9
SUGGESTED
RESISTOR
R2 kΩ (1% tol)
40.2 or Any
40.2
49.9
30.1
30.9
49.9
53.6
73.2
243
ADDRESS 7'b
0x0C
0x0D
0x0E
0x0F
0x10
0x13
0x14
0x15
0x1B
ADDRESS 8'b
APPENDED
0x18
0x1A
0x1C
0x1E
0x20
0x26
0x28
0x2A
0x36
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