DS90UH925Q-Q1 Datasheet, PDF (27/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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7.6 Register Maps
ADD
(dec)
0
ADD
(hex)
REGISTER
NAME
0x00 I2C Device ID
1
0x01 Reset
3
0x03 Configuration
[0]
DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Table 6. Serial Control Bus Registers
Bit(s)
7:1
0
7
6:2
1
0
7
6
5
4
3
2
1
0
REG-
ISTER
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x00
0xD2
Device ID 7–bit address of Serializer
ID Setting
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
Remote
Auto Power
Down
Remote Auto Power Down
1: Power down when no Bidirectional Control
Channel link is detected
0: Do not power down when no Bidirectional Control
Channel link is detected
Reserved.
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
Back
channel
CRC
Checker
Enable
Back Channel Check Enable
1: Enable
0: Disable
Reserved.
I2C Remote Automatically Acknowledge I2C Remote Write
Write Auto When enabled, I2C writes to the Deserializer (or
Acknowledg any remote I2C Slave, if I2C PASS ALL is enabled)
e
are immediately acknowledged without waiting for
the Deserializer to acknowledge the write. This
allows higher throughput on the I2C bus
1: Enable
0: Disable
Filter
Enable
HS, VS, DE two clock filter When enabled, pulses
less than two full PCLK cycles on the DE, HS, and
VS inputs will be rejected
1: Filtering enable
0: Filtering disable
I2C Pass-
through
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
Reserved
PCLK Auto Switch over to internal OSC in the absence of PCLK
1: Enable auto-switch
0: Disable auto-switch
TRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising
Clock Edge.
0: Parallel Interface Data is strobed on the Falling
Clock Edge.
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