DS90UH925Q-Q1 Datasheet, PDF (44/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Typical Application (continued)
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HOST
Graphics
Processor
V_DDIO VDD33
(1.8V or 3.3V) (3.3V)
V_DD33 V_DDIO
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
3
I2S AUDIO _/
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair /AC Coupled
0.1 2F
0.1 2F
DOUT-
DS90UH925Q-Q1
Serializer
DAP
100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UH926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
3
/
I2S AUDIO
(STEREO)
MCLK
RGB Display
720p
24-bit color depth
DAP
Figure 24. Typical Display System Diagram
8.2.1 Design Requirements
For the typical desing application, use the following as input parameters.
Table 7. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for DOUT±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
100 nF
85 MHz
8.2.2 Detailed Design Procedure
Figure 23 shows a typical application of the DS90UH925Q-Q1 serializer for an 85 MHz 24-bit Color Display
Application. The CML outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines.
The serializer has an internal termination. Bypass capacitors are placed near the power supply pins. At a
minimum, six (6) 4.7μF capacitors (and two (2) additional 1μF capacitors should be used for local device
bypassing. Ferrite beads are placed on the two (2) VDDs (V_DD33 and V_DDIO) for effective noise suppression. The
interface to the graphics source is with 3.3V LVCMOS levels, thus the V_DDIO pin is connected to the 3.3 V rail. A
RC delay is placed on the PDB signal to delay the enabling of the device until power is stable.
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