DS90UH925Q-Q1 Datasheet, PDF (13/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

www.ti.com
6.10 Typical Charateristics
DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Time (1.25 ns/DIV)
Note: On the rising edge of each clock period, the CML driver
outputs a low Stop bit, high Start bit, and 33 DC-scrambled data
bits.
Figure 9. Serializer CML Driver Output
with 78 MHZ TX Pixel Clock
78 MHz TX
Pixel Clock
Input
(2 V/DIV)
78 MHz RX
Pixel Clock
Output
(2 V/DIV)
Time (10 ns/DIV)
Figure 10. Comparison of Deserializer LVCMOS RX PCLK
Output Locked to a 78 MHz TX PCLK
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS90UH925Q-Q1
Submit Documentation Feedback
13