DS90UH925Q-Q1 Datasheet, PDF (16/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
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Feature Description (continued)
7.3.6 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power disable the link when the display
is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO
have reached final levels; no external components are required. In the case of driven by the V_DDIO = 3.0V to 3.6V
or V_DD33 directly, a 10 kohm resistor to the V_DDIO = 3.0V to 3.6V or V_DD33 , and a >10uF capacitor to the ground
are required see Figure 23.
7.3.7 Remote Auto Power Down Mode
The Serializer features a remote auto power down mode. During the power down mode of the pairing
deserializer, the Serializer enters the remote auto power down mode. In this mode, the power dissipation of the
Serializer is reduced significantly. When the Deserializer is powered up, the Serializer enters the normal power
on mode automatically. This feature is enabled through the register bit 0x01[7] Table 6.
7.3.8 LVCMOS V_DDIO Option
1.8V or 3.3V Inputs and Outputs are powered from a separate V_DDIO supply to offer compatibility with external
system interface signals. Note: When configuring theV_DDIO power supplies, all the single-ended data and control
input pins for device need to scale together with the same operating V_DDIO levels.
7.3.9 Input PCLK Loss Detect
The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A
clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again,
the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registers
values are still RETAINED.
7.3.10 Serial Link Fault Detect
The serial link fault detection is able to detect any of following seven (7) conditions
1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked correctly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address
0x0C Table 6.
7.3.11 Pixel Clock Edge Select (RFB)
The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines
the edge that the data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB
is LOW (‘0’), data is latched on the Falling edge of the PCLK.
7.3.12 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency
of the serializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is
High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,
a PDB reset is required.
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