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| DS90UH925Q-Q1 Datasheet, PDF (37/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP | |||
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www.ti.com
DS90UH925Q-Q1
SNLS336J â OCTOBER 2010 â REVISED NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
192
ADD
(hex)
REGISTER
NAME
0xC0 HDCP DBG
Table 6. Serial Control Bus Registers (continued)
Bit(s)
7:4
3
2
1
0
REG-
ISTER
TYPE
RW
RW
RW
RW
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x00
Reserved
RGB
CHKSUM
Enable RGB video line checksum
Enables sending of ones-complement checksum for
each 8-bit RBG data channel following end of each
video data line
Fast LV
Fast Link Verification
HDCP periodically verifies that the HDCP Receiver
is correctly synchronized. Setting this bit will
increase the rate at which synchronization is
verified. When set to a 1, Pj is computed every 2
frames and Ri is computed every 16 frames. When
set to a 0, Pj is computed every 16 frames and Ri is
computed every 128 frames.
TMR Speed Timer Speedup
Up
Speed up HDCP authentication timers.
HDCP I2C
Fast
HDCP I2C Fast Mode Enable
Setting this bit to a 1 will enable the HDCP I2C
Master in the HDCP Receiver to operate with Fast
mode timing. If set to a 0, the I2C Master will
operate with Standard mode timing. This bit is
mirrored in the IND_STS register
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