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DS90UH925Q-Q1 Datasheet, PDF (1/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP
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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
DS90UH925Q-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP
1 Features
•1 Integrated HDCP Cipher Engine with On-chip Key
Storage
• Bidirectional Control Interface Channel Interface
with I2C Compatible Serial Control Bus
• Supports High Definition (720p) Digital Video
Format
• RGB888 + VS, HS, DE and I2S Audio Supported
• 5 to 85 MHz PCLK Supported
• Single 3.3V Operation with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
• AC-coupled STP Interconnect up to 10 meters
• Parallel LVCMOS Video Inputs
• DC-balanced & Scrambled Data with Embedded
Clock
• HDCP Content Protected
• Supports HDCP Repeater Application
• Internal Pattern Generation
• Low Power Modes Minimize Power Dissipation
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
• > 8k V HBM and ISO 10605 ESD rating
• Backward Compatible Modes
2 Applications
• Automotive Display for Navigation
• Rear Seat Entertainment Systems
3 Description
The DS90UH925Q-Q1 serializer, in conjunction with
the DS90UH926Q-Q1 deserializer, provides a
solution for secure distribution of content-protected
digital video within automotive entertainment
systems. This chipset translates a parallel RGB Video
Interface into a single pair high-speed serialized
interface. The digital video data is protected using the
industry standard HDCP copy protection scheme.
The serial bus scheme, FPD-Link III, supports video
and audio data transmission and full duplex control
including I2C communication over a single differential
link. Consolidation of video data and control over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
The DS90UH925Q-Q1 serializer embeds the clock,
content protects the data payload, and level shifts the
signals to high-speed low voltage differential
signaling. Up to 24 RGB data bits are serialized along
with three video control signals and up to two I2S
data inputs.
EMI is minimized by the use of low voltage differential
signaling, data scrambling and randomization and
spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
DS90UH925Q-Q1 WQFN (48)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VDDIO VDD33
(1.8V or 3.3V) (3.3V)
VDD33 VDDIO
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
3
I2S AUDIO /
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair /AC Coupled
0.1 2F
0.1 2F
DOUT-
DS90UH925Q-Q1
Serializer
DAP
100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UH926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
RGB Display
720p
24-bit color depth
LOCK
PASS
3
/
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.