DS90UH925Q-Q1 Datasheet, PDF (18/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
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DESCRIPTION
1
Enable 18-bit mode
2
GPO_REG8
3
GPO_REG7
4
GPO_REG6
5
GPO_REG5
6
GPO_REG4
Table 2. GPO_REG Enable Sequencing Table
DEVICE
DS90UH925Q-Q1
DS90UH925Q-Q1
DS90UH925Q-Q1
DS90UH925Q-Q1
DS90UH925Q-Q1
DS90UH925Q-Q1
LOCAL
ACCESS
0x12 = 0x04
0x11 = 0x90
0x11 = 0x10
0x11 = 0x09
0x11 = 0x01
0x10 = 0x90
0x10 = 0x10
0x10 = 0x09
0x10 = 0x01
0x0F = 0x90
0x0F = 0x10
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LOCAL
OUTPUT
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
7.3.14.3 I2S Transmitting
In normal 24-bit RGB operation mode, the DS90UH925Q-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC
and I2S_DA. The optionally encrypted and packetized audio information can be transmitted during the video
blanking (data island transport) or during active video (forward channel frame transport). Note: The bit rates of
any I2S bits must maintain one fourth of the PCLK rate. The audio encryption capability is supported per HDCP
v1.3.
7.3.14.3.1 Secondary I2S Channel
In I2S Channel B operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio in
addition to the 3–bit of I2S. The I2S_DB input must be synchronized to I2S_CLK and aligned with I2S_DA and
I2S_WC at the input to the serializer. This operation mode is enabled through either the MODE_SEL pin
(Table 4) or through the register bit 0x12[0] (Table 6). Table 3 below covers the range of I2S sample rates.
SAMPLE RATE (kHz)
32
44.1
48
96
192
32
44.1
48
96
192
32
44.1
48
96
192
Table 3. Audio Interface Frequencies
I2S DATA WORD SIZE (bits)
16
16
16
16
16
24
24
24
24
24
32
32
32
32
32
I2S CLK (MHz)
1.024
1.411
1.536
3.072
6.144
1.536
2.117
2.304
4.608
9.216
2.048
2.822
3.072
6.144
12.288
18
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