DS90UH925Q-Q1 Datasheet, PDF (19/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
7.3.14.4 HDCP
The Cipher function is implemented in the serializer per HDCP v1.3 specification. The DS90UH925Q-Q1
provides HDCP encryption of audiovisual content when connected to an HDCP capable FPD-Link III deserializer
such as the DS90UH926Q-Q1. HDCP authentication and shared key generation is performed using the HDCP
Control Channel which is embedded in the forward and backward channels of the serial link. An on-chip Non-
Volatile Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the
manufacturing process and are not accessible external to the device.
The DS90UH925Q-Q1 uses the Cipher engine to encrypt the data as per HDCP v1.3. The encrypted data is
transmitted through the FPD-Link III interface.
7.3.14.5 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics. Note: BIST not available in backwards compatible mode.
7.3.14.5.1 BIST Configuration and Status
The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or
configuration register (Table 6) through the deserializer. When LFMODE = 0, the pin based configuration defaults
to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can
select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the
pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to
35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 6.
7.3.14.5.1.1 Sample BIST Sequence
See Figure 13 for the BIST mode flow diagram.
Step 1: For the DS90UH925Q-Q1 and DS90UH926Q-Q1 FPD-Link III chipset, BIST Mode is enabled via the
BISTEN pin of DS90UH926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTC
pin.
Step 2: The DS90UH925Q-Q1 serializer is woken up through the back channel if it is not already on. The all
zero pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and
BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low
for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to
determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST
is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
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