DS90UH925Q-Q1 Datasheet, PDF (3/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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5 Pin Configuration and Functions
48-Pin
Package RHS
(Top View)
DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
G2 37
G3 38
G4 39
G5 40
G6 41
G7 42
B0/GPO_REG4 43
B1/I2S_DB/GPO_REG5 44
B2 45
B3 46
B4 47
B5 48
DS90UH925Q-Q1
TOP VIEW
DAP = GND
24 MODE_SEL
23 CMF
22 VDD33
21 PDB
20 DOUT+
19 DOUT-
18 RES1
17 CAPHS12
16 NC
15 RES0
14 CAPP12
13 I2S_CLK/GPO_REG8
PIN
NAME
NUMBER
I/O, TYPE
LVCMOS PARALLEL INTERFACE
R[7:0]
34, 33, 32, 29, I, LVCMOS
28, 27, 26, 25 w/ pull down
G[7:0]
42, 41, 40, 39, I, LVCMOS
38, 37, 36, 35 w/ pull down
B[7:0]
2, 1, 48, 47, I, LVCOS
46, 45, 44, 43 w/ pull down
HS
3
I, LVCMOS
w/ pull down
VS
4
I, LVCMOS
w/ pull down
Pin Functions
DESCRIPTION
RED Parallel Interface Data Input Pins
Leave open if unused.
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1.
GREEN Parallel Interface Data Input Pins
Leave open if unused.
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
BLUE Parallel Interface Data Input Pins
Leave open if unused
B0 can optionally be used as GPO_REG4 and B1 can optionally be used as GPO_REG5.
Horizontal Sync Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
Vertical Sync Input Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
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