DS90UH925Q-Q1 Datasheet, PDF (38/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
www.ti.com
Register Maps (continued)
ADD
(dec)
194
ADD
(hex)
REGISTER
NAME
0xC2 HDCP CFG
Table 6. Serial Control Bus Registers (continued)
Bit(s)
7
6
5
4:3
2
1
0
REG-
ISTER
TYPE
RW
RW
RW
RW
RW
RW
RW
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x80
ENH LV
HDCP
EESS
TX RPTR
ENC Mode
Wait
RX DET
SEL
HDCP AV
MUTE
Enable Enhanced Link Verification
Allows checking of the encryption Pj value on every
16th frame
1: Enhanced Link Verification enabled
0: Enhanced Link Verification disabled
Enables Enhanced Encryption Status Signaling
(EESS) instead of the Original Encryption Status
Signaling (OESS)
1: EESS mode enabled
0: OESS mode enabled
Transmit Repeater Enable
Enables the transmitter to act as a repeater. In this
mode, the HDCP Transmitter incorporates the
additional authentication steps required of an HDCP
Repeater.
1: Transmit Repeater mode enabled
0: Transmit Repeater mode disabled
Encryption Control Mode
Determines mode for controlling whether encryption
is required for video frames
00: Enc_Authenticated
01: Enc_Reg_Control
10: Enc_Always
11: Enc_InBand_Control (per frame)
If the Repeater strap option is set at power-up,
Enc_InBand_Control (ENC_MODE == 11) will be
se-lected. Otherwise, the default will be
Enc_Authenticated mode (ENC_MODE == 00).
Enable 100ms Wait
The HDCP 1.3 specification allows for a 100ms wait
to allow the HDCP Receiver to compute the initial
encryption values. The FPD-Link III implementation
ensures that the Receiver will complete the
computations before the HDCP Transmitter. Thus
the timer is unnecessary. To enable the 100ms
timer, set this bit to a 1.
RX Detect Select
Controls assertion of the Receiver Detect Interrupt.
If set to 0, the Receiver Detect Interrupt will be
asserted on detection of an FPD-Link III Receiver. If
set to 1, the Receiver Detect Interrupt will also
require a receive lock indication from the receiver.
Enable AVMUTE
Setting this bit to a 1 will initiate AVMUTE operation.
The transmitter will ignore encryption status controls
while in this state. If this bit is set to a 0, normal
operation resumes. This bit may only be set if the
HDCP_EESS bit is also set.
38
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