DS90UH925Q-Q1 Datasheet, PDF (4/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
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Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
DE
5
I, LVCMOS Data Enable Input Pin
w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
PCLK
10
I, LVCMOS
w/ pull down
Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6.
I2S_CLK,
I2S_WC,
I2S_DA
13, 12, 11
I, LVCMOS
w/ pull down
Digital Audio Interface Data Input Pins
Leave open if unused.
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
OPTIONAL PARALLEL INTERFACE
I2S_DB
44
Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by
I, LVCMOS MODE_SEL pin or configuration register
w/ pull down Leave open if unused.
I2S_DB can optionally be used as B1 or GPO_REG5.
GPIO[3:0]
36, 35, 26, 25
General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or
I/O, LVCMOS configuration register. See Table 6.
w/ pull down Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[ 13, 12, 11, 44, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 6.
8:4]
43
w/ pull down Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
CONTROL
PDB
21
I, LVCMOS Power-down Mode Input Pin
w/ pull-down PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL
24
I, Analog Device Configuration Select. See Table 4.
I2C
IDx
6
I, Analog I2C Serial Control Bus Device ID Address Select
External pull-up to V_DD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 19.
SCL
8
I/O, LVCMOS I2C Clock Input / Output Interface
Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA
9
I/O, LVCMOS I2C Data Input / Output Interface
Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
4
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