DS90UH925Q-Q1 Datasheet, PDF (45/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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8.2.3 Application Curves
DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Time (100 ps/DIV)
Figure 25. Serializer Eye Diagram with 78 MHz TX Pixel
Clock
Time (2.5 ns/DIV)
Figure 26. Serializer CML Output with 78 MHz TX Pixel
Clock
9 Power Supply Recommendations
This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate
power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between
different sections of the circuit. Separate planes on the PCB are typically not required. Pin description tables
typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an
external filter may be used to provide clean power to sensitive circuits such as PLLs.
9.1 Power Up Requirements and PDB Pin
The VDDs (V_DD33 and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating
voltage. When PDB pin is pulled to V_DDIO = 3.0V to 3.6V or V_DD33, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
All inputs must not be driven until V_DD33 and V_DDIO has reached its steady state value.
9.2 CML Interconnect Guidelines
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: www.ti.com/lvds.
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