DS90UH925Q-Q1 Datasheet, PDF (29/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
Register Maps (continued)
ADD
(dec)
6
7
8
10
11
12
Table 6. Serial Control Bus Registers (continued)
ADD
(hex)
REGISTER
NAME
0x06 DES ID
Bit(s)
7:1
0
0x07 Slave ID
7:1
0
0x08 Slave Alias
7:1
0
0x0A CRC Errors
7:0
0x0B
7:0
0x0C General Status
7:4
3
2
1
0
REG-
ISTER
TYPE
RW
RW
RW
RW
R
R
R
R
R
R
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x00
0X00
0x00
0x00
0x00
0x00
DES Device 7-bit Deserializer Device ID
ID
Configures the I2C Slave ID of the remote
Deserializer. A value of 0 in this field disables I2C
access to the remote Deserializer. This field is
automatically configured by the Bidirectional Control
Channel once RX Lock has been detected.
Software may overwrite this value, but should also
assert the FREEZE DEVICE ID bit to prevent
overwriting by the Bidirectional Control Channel.
Device ID
Frozen
Freeze Deserializer Device ID
Prevents autoloading of the Deserializer Device ID
by the Bidirectional Control Channel. The ID will be
frozen at the value written.
Slave
Device ID
7-bit Remote Slave Device ID
Configures the physical I2C address of the remote
I2C Slave device attached to the remote
Deserializer. If an I2C transaction is addressed to
the Slave Device Alias ID, the transaction will be
remapped to this address before passing the
transaction across the Bidirectional Control Channel
to the Deserializer
Reserved
Slave
Device
Alias ID
7-bit Remote Slave Device Alias ID
Assigns an Alias ID to an I2C Slave device attached
to the remote Deserializer. The transaction will be
remapped to the address specified in the Slave ID
register. A value of 0 in this field disables access to
the remote I2C Slave.
Reserved
CRC Error Number of back channel CRC errors – 8 least
LSB
significant bits
CRC Error Number of back channel CRC errors – 8 most
MSB
significant bits
Reserved
BIST CRC
Error
Back channel CRC error during BIST
communication with Deserializer.
The bit is cleared upon loss of link, restart of BIST,
or assertion of CRC ERROR RESET in register
0x04.
PCLK
Detect
PCLK Status
1: Valid PCLK detected
0: Valid PCLK not detected
DES Error
Back channel CRC error during communication with
Deserializer.
The bit is cleared upon loss of link or assertion of
CRC ERROR RESET in register 0x04.
LINK Detect LINK Status
1: Cable link detected
0: Cable link not detected (Fault Condition)
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