DS90UB913A-Q1 Datasheet, PDF (5/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
Pin Functions: DS90UB913A-Q1 Serializer (continued)
PIN
I/O
NAME
NO.
DESCRIPTION
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]
16,15
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and respond to
various commands. GPO[1:0] can be configured to be the outputs for input signals coming
from GPIO[1:0] pins on the Deserializer or can be configured to be outputs of the local
register on the Serializer. Leave open if unused.
GPO[2]/
CLKOUT
GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pin
17
Output,
LVCMOS
on the Deserializer or can be configured to be the output of the local register on the
Serializer. It can also be configured to be the output clock pin when the DS90UB913A-Q1
device is used in the External Oscillator mode. See Device Functional Modes section for a
detailed description of External Oscillator Mode. Leave open if unused.
GPO[3]/
CLKIN
GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin on
18
Input/Output,
LVCMOS
the Deserializer or can be configured to be the output of the local register setting on the
Serializer. It can also be configured to be the input clock pin when the DS90UB913A-Q1
Serializer is working with an external oscillator. See Device Functional Modes section for a
detailed description of External Oscillator Mode. Leave open if unused.
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
SCL
SDA
MODE
4
Input/Output, Clock line for the bidirectional control bus communication.
Open Drain SCL requires an external pullup resistor to V_DDIO.
5
Input/Output, Data line for the bidirectional control bus communication.
Open Drain SDA requires an external pullup resistor to V_DDIO.
8
Input,
LVCMOS
w/ pulldown
Device mode select.
Resistor (Rmode) to Ground and 10-kΩ pullup to 1.8-V rail. MODE pin on the Serializer can
be used to select whether the system is running off the PCLK from the imager or an external
oscillator. See details in Table 1.
ID[x]
Device ID Address Select.
6
Input, analog The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor (RID) to
Ground and 10-kΩ pullup to 1.8-V rail. See Table 5.
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
Input,
PDB = H, Serializer is enabled and is ON.
9
LVCMOS PDB = L, Serializer is in Power Down mode. When the Serializer is in Power Down, the PLL
w/ pulldown is shutdown, and IDD is minimized. Programmed control register data is NOT retained and
reset to default values.
RES
7
Input,
LVCMOS
w/ pulldown
Reserved.
This pin MUST be tied LOW.
FPD–Link III INTERFACE
DOUT+
13
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect must be
CML
AC Coupled with a 0.1-µF capacitor.
DOUT-
12
POWER AND GROUND⁽¹⁾
Input/Output,
CML
Inverting differential output, bidirectional control channel input. The interconnect must be AC
Coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a
0.047-µF AC coupling capacitor should be placed in series with a 50Ω resistor before
terminating to GND.
VDDPLL
10
Power,
Analog
PLL Power, 1.8 V ±5%.
VDDT
11
Power,
Analog
Tx Analog Power, 1.8V ±5%.
VDDCML
14
Power,
Analog
CML & Bidirectional Channel Driver Power, 1.8 V ±5%.
VDDD
28
Power,
Digital
Digital Power, 1.8 V ±5%.
VDDIO
25
Power,
Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V_DDIO. V_DDIO
can be connected to a 1.8V ±5% or 2.8V ±10% or 3.3V ±10%.
VSS
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at the
center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
(1) See Power-Up Requirements and PDB Pin.
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