DS90UB913A-Q1 Datasheet, PDF (10/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
7.6 Recommended Serializer Timing For PCLK^{(1) (2)}
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
10-bit mode
50 MHz – 100 MHz
10
t_TCP
Transmit Clock Period
12-bit high frequency mode
37.5 MHz - 75MHz
13.33
12-bit low frequency mode
25 MHz - 50MHz
20
t_TCIH
Transmit Clock
Input High Time
0.4T
t_TCIL
Transmit Clock
Input Low Time
0.4T
10-bit mode
50 MHz – 100 MHz
0.05T
t_CLKT
PCLK Input Transition Time 12-bit high frequency mode
(Figure 7)
37.5 MHz - 75MHz
0.05T
12-bit low frequency mode
25 MHz - 50MHz
0.05T
t_JIT0
PCLK Input Jitter
(PCLK from imager mode)
Refer to Jitter freq > f/20
f = 25 – 100
MHz
t_JIT1
PCLK Input Jitter
(External Oscillator mode)
Refer to Jitter freq > f/20
f = 25 – 100
MHz
t_JIT2
External Oscillator Jitter
Refer to Jitter freq > f/20
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
(2) T is the period of the PCLK.
NOM
T
T
T
0.5T
0.5T
0.25T
0.25T
0.25T
0.01T
1T
0.01T
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MAX
20
UNIT
ns
26.67
ns
40
ns
0.6T
ns
0.6T
ns
0.3T
ns
0.3T
ns
0.3T
ns
ns
ns
ns
10
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